Memory devices typically include an array of memory cells that use transistors to store logic states: a logic “1” or “0.” A reference cell can be used to read or verify the proper logic states stored in the memory cells. For instance, the output voltage of a memory cell can be compared with the output voltage of the reference cell and, depending on the comparison of the voltages, one of the stored logic states can thus be determined. In addition, when a memory cell is programmed or erased, the output voltage or signal it generates can differ from the reference voltage by some margin. Thus, generating an accurate reference current (used for generating the reference voltage) is also important in determining that the correct logic state is stored in the memory cells and read at a proper speed.
Over time, memory cells may experience continual erasing and programming that can cause variations of the threshold voltages on the individual memory cells. The threshold voltages determine whether a memory cell properly stores a logic “1” or a “0.” Moreover, the process variations in making a memory device can also induce initial threshold voltage VT differences as well. Prior methods for generating a reference voltage or signal have been deficient in dealing with initial threshold voltage VT variations. For example, FIG. 1A illustrates a prior art reference cell 103 with memory array cells 103. The reference cell 103 can provide a constant reference current (used for generating the reference voltage) by adjusting DC voltage levels on the reference word line (RWL) 123. This reference voltage can be compared with the output voltages of the memory array cells 102 to determine the stored logic state in memory array cells 102. The following table shows the voltage levels used on the word line 122 for memory array cells 102 and reference word line 123 for reference cell 103 during different read modes for the prior scheme.
READ MODESWL VOLTAGESRWL VOLTAGESUser Read modeAVX (4.1 V)RAVX (DC Bias)Program Verify ModeAVX (5.2 V)RAVX (DC Bias)Erase Verify ModeAVX (3.4 V)RAVX (DC Bias)Other Read/Verify ModesAVXRAVX (DC Bias)
Referring to the above table, the prior art scheme did not account for initial threshold voltage VT variations. For instance, to adjust the voltage level on the reference word line 123, the reference cell 103 is maintained at an initial state and does not operate in a programmed or erased state. Thus, all read, program verify, and erase verify modes share the same reference cell 103. By using the same reference cell in this prior scheme, the voltage levels applied to the WL 122 and RWL 123 are different (i.e., non-tracking of the WL/RWL voltage levels). In this manner, the memory array cells 102 and reference cell 103 are activated with different voltage levels that can cause improper voltage levels to be compared with when reading a data bit in the memory array cells 103. As a result, read margin loss can occur if improper data is read from the memory array cells 103.
FIG. 1B illustrates graphically the effects of initial threshold voltage VT variations for the prior memory array cells of FIG. 1A. As shown, the read RD, erase verify EV, and program verify PV voltage levels are fixed. However, different memory devices can have different cycle margins due to varying initial threshold voltages VT. The cycle margin (CM) can be dependent on the process variations and thus affect the reliability of the memory device. Hence, to obtain proper operation of a memory device and maintain superior data reliability and retention, the varying initial threshold voltages VT across the memory cells should be accommodated for when comparing with the reference voltage and reading the logic states stored in the memory cells. The erase margin (EM) is defined by the voltage difference between the RD voltage level and the erase verify EV voltage level. The program margin (PM) is defined by the voltage difference between the RD voltage level and the program verify PV voltage level.
Thus, what is needed is an improved memory device having reference cells providing reference voltages or signals that accommodate for varying initial threshold voltages VT.